ISCA 2024
GeneSys Tutorial | June 29, 2024 | 2:00 PM - 5:30 PM ART | Quebracho A
Overview
This tutorial will present a discussion on emerging deep learning models along with a comprehensive walkthrough of our newly developed system, GeneSys. Attendees will gain valuable insights into our cutting-edge technology and its wide-ranging applications in the field of DNN acceleration systems.
Goals
We aim for attendees to gain a thorough understanding of the functionalities of our innovative system. They will learn how it can be effectively implemented in various applications and be equipped with the knowledge to harness its potential for their own projects and research in deep learning and DNN acceleration systems.
Who Should Attend
Researchers and developers interested in deep learning systems, compiler development, and hardware/software design for DNN acceleration systems.
Logistics
- Venue: ISCA 2024
- Date: June 29, 2024
- Time: 2:00 PM - 5:30 PM ART
- Registration: To secure your spot for our tutorial, please sign up for at least a “Add One Day W/T”. You can register here.
Schedule
Start (EST) | End (EST) | Agenda | Presenter | Resources |
|---|---|---|---|---|
| 2:00 PM | 2:30 PM | Overview/Motivation | Rohan | slides |
| History and challenges of hardware acceleration | ||||
| Inference pipeline – datacenters and edge | ||||
| Systems challenges and opportunities | ||||
| Introduction to GeneSys | ||||
| GeneSys for research | ||||
| GeneSys for teaching | ||||
| 2:30 PM | 3:00 PM | GeneSys Architecture | Rohan | slides |
| GeneSys NPU overview | ||||
| Systolic array | ||||
| On-chip memory architecture and memory interface | ||||
| Tandem processor | ||||
| End-to-end neural network execution | ||||
| ISA | ||||
| 3:00 PM | 3:20 PM | Afternoon Break | ||
| 3:20 PM | 4:30 PM | GeneSys Compiler | Chris | slides |
| Introduction to compilation | ||||
| Compilation challenges for DNN accelerators | ||||
| f-DFG frontend | ||||
| Codelet backend | ||||
| Compiler overview | ||||
| Using the compiler and it to your needs | ||||
| Realities about end-to-end applications | ||||
| FhY: Cross-domain compilation stack for multi-acceleration | ||||
| Demo: Compiling ResNet50, changing tiling, loop order, on-chip buffers, fusing layers | video coming soon… | |||
| 4:30 PM | 5:00 PM | GeneSys Quantization/Verification/Profiling | Rohan | slides |
| Example problem: data motion acceleration | ||||
| Example problem: neuromodulation for brain-implantable devices | ||||
| Quantization with GeneSys | ||||
| Python APIs | ||||
| Performance profiling | ||||
| Software simulator overview | ||||
| Evaluations using GeneSys | ||||
| RTL simulation | ||||
| Hardware emulation | ||||
| FPGA implementation and synthesis |
Presenters
- Rohan Mahapatra: Ph.D. student in computer science and engineering at the University of California, San Diego
- Christopher Priebe: Ph.D. student in computer science and engineering at the University of California, San Diego