MICRO 2023
GeneSys Tutorial | October 29, 2023 | 1:00 PM - 5:00 PM EDT | Harbour Salon A
Overview
This tutorial will present a discussion on emerging deep learning models along with a comprehensive walkthrough of our newly developed system, GeneSys. Attendees will gain valuable insights into our cutting-edge technology and its wide-ranging applications in the field of DNN acceleration systems.
Goals
We aim for attendees to gain a thorough understanding of the functionalities of our innovative system. They will learn how it can be effectively implemented in various applications and be equipped with the knowledge to harness its potential for their own projects and research in deep learning and DNN acceleration systems.
Who Should Attend
Researchers and developers interested in deep learning systems, compiler development, and hardware/software design for DNN acceleration systems.
Logistics
- Venue: MICRO 2023
- Date: October 29, 2023
- Time: 1:00 PM - 5:00 PM EDT
- Registration: To secure your spot for our tutorial, please sign up for at least a “One-Day Workshop/Tutorial” with October 29, 2023 as your preferred date of attendance. You can register here.
Schedule
| Start (EST) | End (EST) | Agenda | Presenter | Resources |
|---|---|---|---|---|
| 1:00 PM | 1:30 PM | Introduction | Hadi | slides |
| DNNs, LLMs, and hardware acceleration Need for open-source toolchain | video | |||
| System overview Potential use cases | video | |||
| 1:30 PM | 1:50 PM | GeneSys Architecture | Rohan | slides |
| Systolic array SIMD array On-chip memory architecture and memory interface | video | |||
| Tiled execution | video | |||
| 1:50 PM | 2:30 PM | GeneSys Verification | Lavanya | slides |
| RTL simulation | video | |||
| Hardware emulation | video | |||
| FPGA implementation and synthesis | video | |||
| Python driver | video | |||
| Interactive Activity: Configuring GeneSys 16x16; observe it is 16x16; run a single layer | ||||
| Interactive Activity: Configuring GeneSys 4x4; observe it is 4x4; run same layer | ||||
| Demo: FPGA | ||||
| 2:30 PM | 4:00 PM | Compiler and Programming Model | Chris | slides |
| Compiler overview | video | |||
| 3:00 PM | 3:30 PM | Coffee break | ||
| Interactive Activity: Compiling ResNet50, changing tiling, loop order, on-chip buffers, fusing layers | video coming soon… | |||
| Interactive Activity: Compiling BERT | video coming soon… | |||
| Adding a new layer Compiling to a new target architecture | video | |||
| 4:00 PM | 4:30 PM | Runtime and Drivers | Hanyang | slides |
| Example problem: data motion acceleration Example problem: neuromodulation for brain-implantable devices Challenges and opportunities with a unified runtime Python APIs | video | |||
| 4:30 PM | 5:00 PM | Performance Profiling on GeneSys | Hanyang | slides |
| Software simulator Performance profiling with software simulator | video |
Presenters
- Hadi Esmaeilzadeh: Halicioğlu Chair in computer architecture and professor at the University of California, San Diego
- Rohan Mahapatra: Ph.D. student in computer science and engineering at the University of California, San Diego
- Hanyang Xu: Ph.D. student in computer science and engineering at the University of California, San Diego
- Lavanya Karthikeyan: Lead Design Engineering at Cadence Design Systems
- Christopher Priebe: Ph.D. student in computer science and engineering at the University of California, San Diego