Overview

This tutorial will present a discussion on emerging deep learning models along with a comprehensive walkthrough of our newly developed system, GeneSys. Attendees will gain valuable insights into our cutting-edge technology and its wide-ranging applications in the field of DNN acceleration systems.

Goals

We aim for attendees to gain a thorough understanding of the functionalities of our innovative system. They will learn how it can be effectively implemented in various applications and be equipped with the knowledge to harness its potential for their own projects and research in deep learning and DNN acceleration systems.

Who Should Attend

Researchers and developers interested in deep learning systems, compiler development, and hardware/software design for DNN acceleration systems.

Logistics

Venue: HPCA 2024
Date: March 2, 2024
Time: 1:40 PM - 6:00 PM GMT
Registration: To secure your spot for our tutorial, please sign up for at least a “One-Day Workshop/Tutorial” with March 2, 2024 as your preferred date of attendance. You can register here.

Schedule

Start (EST)	End (EST)	Agenda	Presenter	Resources
1:40 PM	2:00 PM	Introduction	Hadi	slides
		History and challenges of hardware acceleration
		Introduction to GeneSys
		GeneSys for research
		GeneSys for teaching
2:00 PM	2:30 PM	Motivation	Rohan	slides
		Neural networks and hardware acceleration
		Inference pipeline – datacenters and edge
		Systems challenges and opportunities
		Overview of GeneSys
		Example usage of GeneSys in research projects
2:30 PM	3:40 PM	GeneSys Architecture and Verification	Rohan	slides
		GeneSys NPU architecture
		ISA
		End-to-end neural network execution
		Verification methodology
		FPGA implementation on AWS
		Demo: Configuring and generating an NPU
		Demo: Adding a new compute unit
		Demo: Adding a new instruction
3:40 PM	4:00 PM	Coffee break
3:30 PM	5:00 PM	GeneSys Compiler	Chris	slides
		General-purpose and DNN compilers overview
		Compilation challenges for DNN accelerators
		f-DFG frontend
		Codelet backend
		Compiler overview
		Tailoring the compiler to your needs
		Demo: Compiling ResNet50, changing tiling, loop order, on-chip buffers, fusing layers		video coming soon…
5:00 PM	5:30 PM	Runtime and Drivers	Chris	slides
		Example problem: neuromodulation for brain-implantable devices
		Challenges and opportunities with a unified runtime
		Python APIs
5:30 PM	6:00 PM	GeneSys Software Simulator	Rohan	slides
		Performance profiling
		Software simulator overview
		Validation with FPGA
		Evaluations using GeneSys

Presenters

Hadi Esmaeilzadeh: Halicioğlu Chair in computer architecture and professor at the University of California, San Diego
Rohan Mahapatra: Ph.D. student in computer science and engineering at the University of California, San Diego
Christopher Priebe: Ph.D. student in computer science and engineering at the University of California, San Diego