ASPLOS 2024
GeneSys Tutorial | April 28, 2024 | 1:30 PM - 5:00 PM PST | Grande D
Overview
This tutorial will present a discussion on emerging deep learning models along with a comprehensive walkthrough of our newly developed system, GeneSys. Attendees will gain valuable insights into our cutting-edge technology and its wide-ranging applications in the field of DNN acceleration systems.
Goals
We aim for attendees to gain a thorough understanding of the functionalities of our innovative system. They will learn how it can be effectively implemented in various applications and be equipped with the knowledge to harness its potential for their own projects and research in deep learning and DNN acceleration systems.
Who Should Attend
Researchers and developers interested in deep learning systems, compiler development, and hardware/software design for DNN acceleration systems.
Logistics
- Venue: ASPLOS 2024
- Date: April 28, 2024
- Time: 1:30 PM - 5:00 PM PST
- Registration: To secure your spot for our tutorial, please sign up for at least a “One-day Workshops/Tutorials Registration”. You can register here.
Schedule
| Start (EST) | End (EST) | Agenda | Presenter | Resources |
|---|---|---|---|---|
| 1:30 PM | 1:50 PM | Introduction | Hadi | slides |
| History and challenges of hardware acceleration Introduction to GeneSys | video | |||
| 1:50 PM | 2:00 PM | Motivation | Rohan | slides |
| Neural networks and hardware acceleration Inference pipeline – datacenters and edge Systems challenges and opportunities Overview of GeneSys Example usage of GeneSys in research projects | video | |||
| 2:00 PM | 3:00 PM | GeneSys Architecture | Soroush | slides |
| GeneSys NPU overview Systolic array On-chip memory architecture and memory interface Tandem processor End-to-end neural network execution ISA | video | |||
| 3:00 PM | 3:30 PM | Afternoon Break | ||
| 3:30 PM | 4:30 PM | GeneSys Compiler | Chris | slides |
| Introduction to compilation Compilation challenges for DNN accelerators f-DFG frontend Codelet backend Compiler overview Using the compiler and tailoring it to your needs Realities about end-to-end applications FhY: Cross-domain compilation stack for multi-acceleration | video | |||
| Demo: Compiling ResNet50, changing tiling, loop order, on-chip buffers, fusing layers | video coming soon… | |||
| 4:30 PM | 5:00 PM | GeneSys Uses, Verification, and Software Simulator | Hanyang | slides |
| Example problem: data motion acceleration Example problem: neuromodulation for brain-implantable devices Quantization on GeneSys Python APIs Software simulator RTL simulation Validation with FPGA | video |
Presenters
- Hadi Esmaeilzadeh: Halicioğlu Chair in computer architecture and professor at the University of California, San Diego
- Soroush Ghodrati: System Architect at Apple
- Rohan Mahapatra: Ph.D. student in computer science and engineering at the University of California, San Diego
- Hanyang Xu: Ph.D. student in computer science and engineering at the University of California, San Diego
- Christopher Priebe: Ph.D. student in computer science and engineering at the University of California, San Diego